In this project, I designed an FPGA hardware implementation of Edge Detection
using Sobel Operator. We have also demonstrated the use of FPGA as hardware accelerator to
offload compute intensive tasks from General Purpose Processor. We have developed a fully
parameterised IP core for edge detection using Sobel Operator. Hardware testing and
demonstration on input 100×100 input image is performed on DE1-SoC board with Cyclone V
FPGA. Testing methodologies for verifying correct working of the module is discussed and
additional methodologies for further testing and improvements is also discussed. Increase in
performance when using an FPGA is analysed.
Hardware Usage – DE1-SoC
Software Usage – Intel Quartus Prime
Language/Skill – VHDL / FPGA
Complete Project Report – Technical_Report
Git Hub Link – Edge Detection
This Project was completed as part of coursework in University of Leeds.